Many circuit blocks require analog input or reference signals for their operation. At the same time, they load these input and/or reference signals in a capacitive and/or resistive way. In many cases, capacitive loading is the more important of the two as it determines the dimensioning of the circuit. Typical examples include Switched Capacitor (SC) circuits. However, even Continuous Time (CT) circuits are often determined by the size of capacitors since quite frequently such establishes the noise limit of the circuit. These capacitive loads usually have to be driven by some amplifier or buffer circuit, which requires compensation to achieve satisfactory stability.
FIG. 1 shows a typical circuit configuration 100 for achieving compensation and including a single stage Operational Transconductance Amplifier (OTA) as a buffer. For a single-stage amplifier—that is, an amplifier having only one high-gain node located at the output—the compensation usually is done at the output node 102. This compensation is accomplished by a technique referred to as “load compensation.” Load compensation utilizes a capacitor 104 connected to the output (i.e., high-gain node) 102. Such structures are known to have good power efficiency and as a rule of thumb they require a transconductance current about 1 μA/MHz/pF. In many cases, the amplification of a single-stage amplifier is insufficient or the output is driven by a special driver stage. In this case, the high-gain node(s) are located internally (i.e., not at the output) to the circuit, and the compensation is done internally as well. Such compensation is often referred to as “internal compensation.”
FIG. 2 shows a typical example of an internal compensation circuit, commonly known as a Miller Amplifier 200. The Miller Amplifier 200 includes an output node 202. The Miller Amplifier 200 also includes a load capacitance 204 connected to the output node 202, and an internal compensation capacitor 206 connected to a high-gain node 208. The Miller Amplifier 200 design is less power efficient than the circuit 100 of FIG. 1 because the load-compensated OTA of circuit 100 has its transit frequency determined by gm/Cload, wherein gm is the transconductance factor and Cload is the capacitance of the load 104. Thus, some transistor current has to be sufficiently large to give the desired gm.
For the Miller Amplifier 200 of FIG. 2, it is known that the output stage 210 should be approximately three times (3×) faster than the transit frequency, which leads to a gm that is three times (3×) higher than in the previous case (for the same transit frequency). Consequently, approximately three times (3×) the amount of current is needed. As can be seen, with the exception of single-stage OTAs (e.g., circuit 100 of FIG. 1), nearly all practical known circuits use internal compensation. Unfortunately, modern process technologies tend to have limited intrinsic gain factors. This leads to the need to move toward multiple stage amplifiers. Several schemes are known for compensation. However, these have several drawbacks, such as increased power consumption and complicated design. Therefore, research is ongoing. See Xianhong Peng and Willy Sansen; Transconductance with Capacitances Feedback Compensation for Multistage Amplifiers; Solid-State Circuits Conference, 2004, ESSCIRC 2004, Proceeding of the 30th European Volume, 21-23 Sep. 2004 Issue, pp. 143-146.
One circuit that utilizes load compensation is a Low-Dropout (LDO) voltage regulator. However, the relevant capacitor values for such LDO's are usually in the (multi) μF-range and are therefore placed outside the integrated circuit (IC) on a printed circuit board (PCB). This solution is not feasible for non-static conditions such as for voice and data communication. It is also not desirable due to cost of pins and external capacitors.
FIG. 3 shows a general four-stage cascaded amplifier 300. Multi-stage amplifiers having the general structure of exemplary cascaded amplifier 300 are more complex and less stable than single-stage amplifiers described in the prior art and, therefore are more difficult to frequency compensate. Moreover, when using multi-stage amplifiers, it is typically desired to generate meaningful amplification at each stage. For example, it may be desired in a given circuit to achieve 40 dB at each amplifier stage of a four-stage amplifier in order to result in 160 dB of gain overall.
FIG. 4 depicts a Bode plot 400 corresponding to the cascaded amplifier 300 of FIG. 3. Traditionally, amplifiers exhibiting 40-80 dB per stage were quite easy to create and the number of stages could be limited to one or a few stages. However, more recent process developments have made achieving 40 dB or higher in a single stage quite difficult. Moreover, if an amplifier stage is to have 40 dB of gain and the stage exhibits a corner frequency of 1 MHz and a unity gain bandwidth of 100 MHz, this leads to an unstable amplifier with a corner frequency (i.e., pole) of 1 MHz at each amplifier stage. Satisfactory stability requires an amplifier structure and compensation method that has only one dominant pole situated at the frequency below 100 MHz.